yosyshq.net
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Official home of Yosys, the open-source Verilog RTL synthesis framework, offering documentation, tutorials, and examples to help FPGA/ASIC designers build and optimize circuits with Yosys and related tools.
More resources on VLSI & FPGA
zipcpu.com
ZipCPU.com is a resource hub for open-source CPU cores and FPGA design, providing Verilog/VHDL source code, design notes, and tutorials. It covers building, simulating, and integrating CPU cores and peripherals in FPGA projects.
FPGA4Fun
A long-running collection of hands-on FPGA projects with full source: VGA output, Pong, PWM audio, and interfaces for RS-232, I2C, SPI, SD card, and HDMI. Includes Verilog and VHDL primers alongside each build.
Nandland
Russell Merrick's FPGA tutorial site, pairing written lessons with videos across FPGA-101 fundamentals, VHDL, and Verilog. Examples target the low-cost Go Board, so beginners can run each design on real hardware rather than simulation alone.
VLSI CAD Part I: Logic
Rob Rutenbar's Coursera course on the algorithms inside chip design tools, covering computational Boolean algebra, BDDs, satisfiability-based verification, and two-level and multi-level logic synthesis. You finish able to explain how a synthesis tool actually transforms logic.
Digital Systems: From Logic Gates to Processors
A UAB course building digital design from combinational logic and finite state machines up to a simple processor, using VHDL and educational CAD tools. Ends with a working understanding of instruction sets, microprograms, and machine-level operation.
CMOS VLSI Design
The standard graduate text on CMOS circuit and system design, covering MOS device behavior, static and dynamic logic families, interconnect, timing, power, memory arrays, and testing. Works as both a course book and a practicing designer's reference.